1. Field of the Invention
The present invention relates to a semiconductor device having a vertical MOS transistor with a trench gate structure and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, a wide variety of mobile devices have been distributed. As power sources for those mobile devices, Li-ion batteries have been heavily used, which have high energy density without generating memory effect. Along therewith, a protection IC for detecting overcharge and overdischarge of the Li-ion battery has become essential. For example, a Li-ion battery for mobile phones has a battery voltage of about 3.6 V, but a voltage of 20 V or more may be applied during charging. Accordingly it is required that the IC includes an element having a high breakdown voltage.
In this case, when a CMOS transistor process is used to satisfy the specification of the above-mentioned IC, it is necessary that the process can form a MOS transistor suitable for low voltage use and a MOS transistor suitable for high voltage use. This is because, the final chip size increases when the entire IC is formed of high breakdown voltage elements since the high breakdown voltage element needs to have a certain element size in order to satisfy its specification, with the result that the IC has no cost-competitiveness, and it becomes difficult to satisfy the demand for market price. Consequently the chip size is reduced by using high breakdown voltage elements in circuit areas to which a high voltage is applied, and using low breakdown voltage elements in other circuit areas. Further, when a power MOSFET is used for the protection IC, the demand for the on-resistance of the power MOSFET is as low as about 10 mΩ·mm2. Since the power MOSFET occupies a much part of the entire chip, the performance improvement of the power MOSFET significantly contributes to the reduction in chip size.
When focusing on the power MOSFET, there has been proposed a MOS transistor having a structure in which a trench is used to form a vertical channel as illustrated in FIG. 3. In the conventional vertical MOS transistor, as a drain region, an N-type buried layer 302 and an N-type epi-layer 303 for relaxing an electric field are formed on a P-type semiconductor substrate 301. Further on a surface thereof, a P-type body region 304, an N-type source high concentration region 306 as a source, and a P-type body contact region 307 are formed by ion implantation, thermal diffusion, and the like. Then, from a surface thereof, a trench 308 reaching the N-type epi-layer 303 is formed, and a side wall of the trench 308 is formed as a gate insulating film 310. Further, a gate electrode 311 is filled in the trench 308. Note that, an insulating film is formed on the gate electrode 311 for insulation with respect to the N-type source high concentration region 306, and the N-type source high concentration region 306 and the P-type body contact region 307 are electrically connected to each other by a source electrode formed on the insulating film. In this vertical MOS transistor, a part of the P-type body region 304 in the vicinity of the gate insulating film 310, which is sandwiched between the N-type epi-layer 303 and the N-type source high concentration region 306, becomes a channel. The current path is therefore vertical, and high integration is possible while maintaining the breakdown voltage. Accordingly, as compared to a lateral MOS transistor having a lateral channel, a lower resistance can be obtained when the transistor is turned ON.
Further, as a method of reducing the on-resistance in the vertical MOS transistor, there are such methods of increasing the concentration of the N-type epi-layer 303 of the drain, or locating the gate electrode closer to the N-type buried layer 302 of the drain. However, in any of those cases, the element on-resistance and the gate-drain breakdown voltage have a trade-off relationship, and hence there has been a problem in that a comprehensive performance improvement becomes difficult.
To address this problem, Japanese Published Patent Application 2002-299619 discloses a structure capable of improving the breakdown voltage while suppressing the increase in on-resistance. As illustrated in FIG. 4, a gate insulating film having two different thicknesses is formed so that a gate insulating film 312 at a bottom portion of the trench is thicker than a gate insulating film at a side surface thereof, to thereby improve the breakdown voltage between the drain and the gate. As an example of a method of forming the gate insulating film having two different thicknesses, a thin gate insulating film and a thin nitride film are formed on an inner surface of the trench, and deposition of an insulating film and etching are repeated so that a second trench is further formed in the trench. In this manner, a thick gate insulating film and a thin gate insulating film are formed in the trench.
However crystal defects are easily generated due to strain stress at the boundary between the thick gate oxide film and the thin gate oxide film since a stepped oxide film is formed. As a result, as compared to an oxide film having no thickness boundary, the long-term reliability of the gate oxide film may be degraded.